Overview   We recognize that packaging has a significant effect on device and system performance, as interconnection densities increase and off-chip speeds span into the GHz range. With today's accelerated development of smaller, more powerful, and higher-speed devices, packaging technology is even more important than in the past. ASE Korea's design and characterization teams are instrumental in making sure the product's performance needs are met. IC package co-design is emphasized at ASE Korea to ensure the packages are designed in concert with the end product's performance and application needs. Technologies in the Spotlight   Highly Integrated Packaging   The need for high density, high performance and cost effectiveness has accelerated the development and application of system in package (SiP). SiP can integrate the different functions of chips in a single package, instead of mounting individual packages onto a large board. ASE Korea can provide integrated modules which use laminate substrate to form copper trace and via as one of the most popular SiP. And also ceramic substrate based modules are available to provide system level solutions in a single package for higher performance and cost effectiveness. Fine Pitch Wirebonding   Wire bond interconnection has been widely used in IC packaging. The advanced technique in wire bonding enhances and extends the use of wire bond to cutting edge packages. Ultra-fine pitch made its debut out of the requirement from chip size shrinking. The continuous shrinking of chip dimensions poses a tough task for IC packagers. Process control, bonding tool design, and bonding diagram layout are the main concerns. ASE Korea upgrades the fine pitch capability day after day and ensures the process stability in mass production. Laser Technology Application   With current advances in industrial technology, the need for precise laser processing has risen dramatically. The ability to control depth in microns with laser can provides an easy and cost effective method for removing excess material, oxide coatings, and providing controlled depth cavities. We're approaching this technology for network marking system, ball scanning, laser de-flashing, and tooling for micro unit equipment. 3D Packages    The demand for low cost, small size, and more functionality has become the main driving force in the electronic industry. To achieve such goals, packaging engineers have developed advanced packaging techniques like 3D packages. The 3D concept is to integrate dies, packages, passive components into one package, in other words, to achieve system in a package (SiP) solution. The integration can be made in side-by-side, stacked, or both manners. The outstanding advantages of 3D package are small footprint, high performance and low cost. To choose from various 3D packaging methods is dependent on the requirement of customers and also by the characteristics of product itself. In ASE Korea, we not only offer various 3D packages but also integrate our experiences and technique to provide total turnkey solutions to our customers to fulfill any requirement and needs. MEMS Packaging    MEMS technology has broadly expanded in the last decade to become the standard for automotive, medical, telecommunications, and consumer electronic applications. Today packaging technology is a bottleneck for MEMS products because these devices need environmental protection, electrical signal integrity, mechanical support and thermal management. In addition, the devices are influenced by chemical or biological environments they interact with. The different application environments require quite different packaging solutions. Based upon the packaging, expertise, ASE Korea performs on identifying potential modification of existing packaging solutions or even assists the customer from the initial device concept via package development to the final product. This includes standard packages like ceramic packages as well as premolded packages and cavity packages based on a fixed set tooling. EMI Protection Technology      As tendency is toward system in package (SIP) and very large-scale integrated circuit (VLSI), the distance between packages has become to be closer. This highly integrated structure gives a rise in interference phenomenon and this will be resulted in wrong action. So, the method for protecting interference is needed and one of those methods is named electromagnetic interference (EMI) protection technology. Because the field created in one package affects another package like right figure, this coupling effect will be decreased by proper standard. Currently the development related that is being preceded. These days EMI solution is more emphasized by growing handset market and Ubiquitous technology. And with patent activity related with EMI technology, try to getcompetitive power of EMI technology area.     Flip Chip Technology   Flip chip technology has its name by flipping over the chip to connect with the substrate. Unlike conventional interconnection through wire bonding, flip chip uses solder or gold bumps instead. Therefore, the I/O pads can be distributed all over the surface of the chip, not only on the peripheral region. The chip size can be shrunk, and the circuit path can be optimized. Additionally, no bonding wire means no wire inductance.  _ Advantages :   Shorter assembly cycle time - flip Chip technology completes all the bonding in one operation. High density & smaller die size - area array pad layout increases I/O density or shrinks the die size. Good electrical performance - Shortest path improves the electrical performance. Direct thermal dissipation path available - external heat sink can be directly added to the chip. Lower packaging profile - without wire and molding, flip chip packages feature lower profile.  _ Capability   Wafer size from 100mm to 200mm diameter Bumped wafer back grinding available to around   200um l Bump metallurgy: SnPb37, SnAg2.5, Sn5Pb95,    SnCu0.7, Pillar bump, etc. l Full area array pitch to 200um, perimeter pad   pitch to 115um  _ Line-up   Flip Chip Image Sensor :   The flip chip interconnect is being used in a camera   image sensor module.   ASE Korea offers the widest application of flip chip   packaging solutions. Flip Chip LTCC / Integrated Module :   This advanced IC package technology allows   application and design engineers to optimize   innovations on handset design while maximizing   the RF performance characteristics. ASE Korea's SiPs are designed for low inductance, enhanced SMT-ability and custom designs with flip chip technology along with long-term reliable operations.   I/O Pkg size(mm) Substrate FC-Module 20~100 3x3~13x13 4~8 layer HDI substrate FC-LTCC 20~100 3x3~13x13 Ceramic FC-Image sensor 20~50 3x3~5x5 2~6 layer laminate