Flip chip derived its name from the method of flipping over the chip to connect with the substrate or leadframe. Unlike conventional interconnection through wire bonding, flip chip uses solder or gold bumps. Therefore, the I/O pads can be distributed all over the surface of the chip and not only on the peripheral. The chip size can be shrunk, and the circuit path, optimized. Another advantage of flip chip is the absence of bonding wire and thus reducing signal inductance.

An essential process for flip chip packaging is wafer bumping. Wafer bumping is an advanced Packaging technique where 'bumps' or 'balls' made of solder are formed on the wafers before being diced into individual chips. ASE has invested significantly in the research and development as well as in equipment for wafer bumping. It has the capacity to bump 150mm, 200mm, 300mm wafers.

Flip chip technology is gaining popularity due to:
， Shorter assembly cycle time - All the bonding for flip chip packages are completed in one process.
， Higher signal density & smaller die size - Area array pad layout increases I/O density. Also, based on the same number of I/Os, the size of the die can be significantly shrunk.
， Good electrical performance - Shorter path between die and substrate improves the electrical performance.
， Direct thermal dissipation path - External heat sink can be directly added to the chip to remove the heat.
， Lower packaging profile - Absence of wire and molding allows flip chip packages to feature lower profiles.

- High Speed Memory
- Power Regulator
- Analog Device (RF)
- Graphic
- Chipset
- Microprocessor
- Communication

， Shorter signal / power/ ground inductance
  As the interconnect is much shorter in length (0.1mm vs. 1-5mm), the inductance of the signal path is greatly reduced. This is a key factor in high speed and switching devices.
  Power can be brought directly into the core of the die by using flip chip interconnect, rater than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon.
， Higher signal density
  Because flip chip can connect over the surface of the die, it can support vastly large numbers of interconnects on the same die size.
， Die shrinkage - for pad limited die
  For pad limited die ( die where size is determined by the edge space required for bond pads), the size of the die can be reduced, saving silicon cost.
， Reduced package footprint
  Total package size can be reduced by using flip chip. This can be achieved by either reducing the die to package edge requirements, since no extra space is required for wires, or in utilizing higher density substrate technology, which allows for reduced package pitch.